IntroductionΒΆ
Warning
This project is a proposal for a SymbiFlow command-line Interface, but is not directly related, neither endorsed, by it.
The SymbiFlow CLI proyect aims to provide a CLI utility to solves HDL-to-bitstream for FPGAs, based on FLOSS:
Yosys is employed for the Synthesis of Verilog code, while NextPnR to perform Place and Route.
GHDL and the ghdl-yosys-plugin provide the VHDL support.
Tools from the IceStorm and Trellis projects provide support for iCE40 and ECP5 devices.
Ideally, it will also support System Verilog (through Surelog and UHDM), other P&R tools (such as VPR), and more devices (employing projects such as Apicula, Mistral, Oxide, XRay, URay, and more!).
Note
By default, it assumes that the tools employed under the hood are installed and ready to be used. Alternatively, an OCI engine such as Docker or Podman could be used, based on containers from the hdl/containers Project.