API Reference

Base class that implements agnostic methods to deal with FPGA projects.

class pyfpga.project.Project(project=None, odir='results')

Base class to manage an FPGA project.

Parameters:

• project (str, optional) – project name (tool name when nothing specified)

• odir (str, optional) – output directory

add_cons(path)

Add a constraint file.

Parameters:

pathname (str) – path of a file

Raises:

FileNotFoundError – if path is not found

add_define(name, value)

Add a Verilog Defile Value.

Parameters:

• name (str) – define name

• value – define value

add_fileset(pathname)

Add fileset file/s.

Parameters:

pathname (str) – path to a fileset file

Raises:

FileNotFoundError – when pathname is not found

add_hook(stage, hook)

Add a hook in the specific stage.

A hook is a place that allows you to insert customized code.

Parameters:

• stage (str) – where to insert the hook

• hook (str) – a tool-specific command

Raises:

ValueError – when stage is invalid

add_include(path)

Add an Include path.

Specify where to search for Included Verilog Files, IP repos, etc.

Parameters:

path – path of a directory

Raises:

NotADirectoryError – if path is not a directory

add_param(name, value)

Add a Parameter/Generic Value.

Parameters:

• name (str) – parameter/generic name

• value – parameter/generic value

add_slog(pathname)

Add System Verilog file/s.

Parameters:

pathname (str) – path to a SV file (glob compliant)

Raises:

FileNotFoundError – when pathname is not found

add_vhdl(pathname, lib=None)

Add VHDL file/s.

Parameters:

• pathname (str) – path to a SV file (glob compliant)

• lib (str, optional) – VHDL library name

Raises:

FileNotFoundError – when pathname is not found

add_vlog(pathname)

Add Verilog file/s.

Parameters:

pathname (str) – path to a SV file (glob compliant)

Raises:

FileNotFoundError – when pathname is not found

make(first='cfg', last='bit')

Run the underlying tool.

Parameters:

• first (str, optional) – first step

• last (str, optional) – last step

Raises:

• ValueError – for missing or wrong values

• RuntimeError – error running the needed underlying tool

Note

valid steps are cfg, syn, par and bit.

prog(bitstream=None, position=1)

Program the FPGA

Parameters:

• bitstream (str, optional) – bitstream to be programmed

• position (str, optional) – position of the device in the JTAG chain

Raises:

• ValueError – for missing or wrong values

• RuntimeError – error running the needed underlying tool

set_debug()

Enables debug messages.

set_part(name)

Set the FPGA part name.

Parameters:

name (str) – FPGA part name

set_top(name)

Set the name of the top level component.

Parameters:

name (str) – top-level name