API Reference

fpga.project

This module implements the main class of PyFPGA, which provides functionalities to create a project, generate a bitstream and transfer it to a Device.

class fpga.project.Project(tool='vivado', project=None, init=None, relative_to_script=True)

Class to manage an FPGA project.

Parameters

• tool – FPGA tool to be used

• project – project name (the tool name is used if none specified)

• init – a dict to initialize some parameters

• relative_to_script – specifies if the files/directories are relative to the script or the execution directory

Raises

NotImplementedError – when tool is unsupported

Note

Valid values for tool are ghdl, ise, libero, openflow, quartus, vivado, yosys, yosys-ise and yosys-vivado

add_files(pathname, filetype=None, library=None, options=None)

Adds files to the project.

Parameters

• pathname – a relative path to a file, which can contain shell-style wildcards (glob compliant)

• filetype – specifies the file type

• library – an optional VHDL library name

• options – to be provided to the underlying tool

Raises

• FileNotFoundError – when a file specified as pathname is not found

• ValueError – when filetype is unsupported

Note

Valid values for filetype are vhdl, verilog,

system_verilog, constraint (default) and block_design (only Vivado is currently supported). If None provided, this value is automatically discovered based on the extension ( .vhd or .vhdl, .v and .sv).

add_hook(hook, phase='project')

Adds a hook in the specified phase.

A hook is a place that allows you to insert customized programming.

Parameters

• hook – is a string representing a tool specific command

• phase – the phase where to insert a hook

Raises

ValueError – when phase is unsupported

Note

Valid values for phase are prefile (to add options needed to find files), project (to add project related options), preflow (to change options previous to run the flow), postsyn (to perform an action between syn and imp), postimp (to perform an action between imp and bit) and postbit (to perform an action after bit)

Warning

Using a hook, you will be probably broken the vendor independence

add_path(path)

Add a search path.

Useful to specify where to search Verilog Included Files or IP repositories.

Parameters

path – a relative path to a directory

Raises

NotADirectoryError – when path is not a directory

clean()

Clean the generated project files.

generate(to_task='bit', from_task='prj', capture=False)

Run the FPGA tool.

Parameters

• to_task – last task

• from_task – first task

• capture – capture STDOUT and STDERR

Returns

STDOUT and STDERR messages

Raises

• ValueError – when from_task is later than to_task

• RuntimeError – when the tool to be used is not found

• ValueError – when to_task or from_task are is unsupported

Note

Valid values for tasks are prj (to creates the project file), syn (to performs the synthesis), imp (to runs implementation) and bit (to generates the bitstream)

get_configs()

Gets the Project Configurations.

Returns

a dict which includes tool and project names, the extension of a project file (according to the selected tool) and the part to be used

get_files()

Get the files of the project.

Returns

a list with the files of the project

set_bitstream(path)

Set the bitstream file to transfer.

Parameters

path – path to the bitstream file

set_outdir(outdir)

Sets the OUTput DIRectory (where to put the resulting files).

Parameters

outdir – path to the output directory

set_param(name, value)

Set a Generic/Parameter Value.

Parameters

• name – parameter/generic name

• value – value to be assigned

set_part(part)

Set the target FPGA part.

Parameters

part – the FPGA part as specified by the tool

set_top(toplevel)

Set the top level of the project.

Parameters

toplevel – name or file path of the top level entity/module

Raises

FileNotFoundError – when toplevel is a not found file

transfer(devtype='fpga', position=1, part='', width=1, capture=False)

Transfers the generated bitstream to a device.

Parameters

• devtype – fpga or other valid option (depending on the used tool, it could be spi, bpi, etc)

• position – position of the device in the JTAG chain

• part – name of the memory (when device is not fpga)

• width – bits width of the memory (when device is not fpga)

• capture – capture STDOUT and STDERR

Returns

STDOUT and STDERR messages

Raises

• RuntimeError – when the tool to be used is not found

• FileNotFoundError – when the bitstream is not found

• ValueError – when devtype, position or width are unsupported