Helpers
hdl2bit
usage: hdl2bit.py [-h] [-v] [-t TOOL] [-o PATH] [-p PART] [-f FILE[,LIBRARY]]
[-i PATH] [--define DEFINE VALUE] [--param PARAMETER VALUE]
[--project PROJECT] [--last STEP]
TOPLEVEL
A CLI helper utility to transform HDL design files into a bitstream.
positional arguments:
TOPLEVEL the top-level name
options:
-h, --help show this help message and exit
-v, --version show program's version number and exit
-t TOOL, --tool TOOL backend tool to be used [vivado]
-o PATH, --odir PATH where to generate files [results]
-p PART, --part PART the target device
-f FILE[,LIBRARY], --file FILE[,LIBRARY]
add a design file (optionally specifying a VHDL
library)
-i PATH, --include PATH
specify a Verilog Include directory
--define DEFINE VALUE
define and set the value of a Verilog Define
--param PARAMETER VALUE
set the value of a Generic/Parameter of the top-level
--project PROJECT optional PROJECT name
--last STEP last step to perform [bit] (cfg|syn|par|bit)
Supported values of arguments with choices:
* TOOL = diamond|ise|libero|openflow|quartus|vivado
* STEP = cfg|syn|par|bit
Notes:
* PATH and FILE must be relative to the execution directory.
* The default PART name and how to specify it depends on the selected TOOL.
* More than one '--file', '--include' or '--param' arguments can be specified.
prj2bit
usage: prj2bit.py [-h] [-v] [--last STEP] PRJFILE
A CLI helper utility to deal with a vendor FPGA Project file.
positional arguments:
PRJFILE a vendor Project File
options:
-h, --help show this help message and exit
-v, --version show program's version number and exit
--last STEP last step to perform [bit] (syn|par|bit)
bitprog
usage: bitprog.py [-h] [-v] [-t TOOL] [-o PATH] [-d TYPE] [-p POSITION]
[-m NAME] [-w WIDTH]
BITFILE
A CLI helper utility to transfer a bitstream to a supported device.
positional arguments:
BITFILE a bitstream file
options:
-h, --help show this help message and exit
-v, --version show program's version number and exit
-t TOOL, --tool TOOL backend tool to be used [vivado]
-o PATH, --odir PATH where to generate files [results]
-d TYPE, --device TYPE
the target device type [fpga]
-p POSITION, --position POSITION
the device position into the JTAG chain [1]
-m NAME, --memname NAME
memory name for SPI or BPI devices [None]
-w WIDTH, --width WIDTH
memory width for SPI or BPI devices [1]
Supported values of arguments with choices:
* TOOL = diamond|ise|libero|openflow|quartus|vivado
* TYPE = fpga|spi|bpi
* POSITION = 1|2|3|4|5|6|7|8|9
* WIDTH = 1|2|4|8|16|32